Low-voltage MOS birth of new power analysis techniques
Author: Shenzhen Yuan Zhi Electronics Co., Ltd.Time:2018-03-01 16:55:38Views:2667【SML】
Multiphase
synchronous buck converters are topologies for microcontroller (MCU)
and other computationally intensive integrated circuits (ICs), such as
digital signal processors (DSPs) and graphics ...
label:
Multiphase
synchronous buck converters are topologies for microcontroller (MCU)
and other computationally intensive integrated circuits (ICs), such as
digital signal processors (DSPs) and graphics processors (GPUs). In a synchronous buck converter, two power MOSFETs are connected in series to form a half-bridge structure. High-voltage low-voltage MOS technology MOSFET as a single-junction control FET; the lower the MOSFET is a synchronous FET.
The
key point in the evolution of this circuit topology was the
introduction of low-voltage MOS knowledge, the Pentium 4 microprocessor
for low-voltage MOS technology, and the associated ATX12V power supply
specification in 2000 where the power rail (ie, the conversion voltage)
was raised from 5 volts to 12 volts to Microprocessors require a fast current increase. The
resulting duty cycle changes have led to major changes in the
performance of power MOSFETs, as well as the full utilization of
low-voltage MOS knowledge indices such as QGD × RDS (on) and QG × RDS
(on) as power MOSFET performance specifications. However, such FOM and RDS (on) have dropped about tenfold over
the past 10 years in certain size products, and QG and QGD are no longer
the major contributors to power MOSFET power dissipation.
In
the case of a control FET, the parasitic inductance of the MOSFET
package and printed circuit board (PCB) connections can outweigh the
losses caused by the QGD. Reduce
the parasitic inductance needs To promote the popularization of
low-voltage MOS knowledge of Power SO8 package and the concept of
integrated power in 2002 low-voltage MOS knowledge, low-voltage MOS
technology to produce, which means the low-voltage MOS technology
control and synchronous FET and MOSFET driver integrated in a square This concept was adopted by the Intel DrMOS specification in 2004 in a flat leadless package (QFN).
In
response to the multi-faceted power MOSFET loss, a series of
increasingly complex computing methods and efficiency index has been
proposed. In
the area of power mechanism research, the preferred technique is to
make detailed behavioral models using TCAD tools such as TSuprem4 and
Medici, combined with low-voltage MOS knowledge and detailed circuit
simulations of low-voltage MOS techniques such as PSpice to produce
detailed work Consumption analysis results. Although
this method can be used for further analysis of different power
consumption mechanisms, the results of the low-voltage MOS analysis must
be converted into a set of MOSFET-based FOMs for the development of new
technologies.
2018-03-01
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