MOS tube the correct choice of steps
Author: Shenzhen Yuan Zhi Electronics Co., Ltd.Time:2018-03-01 17:15:42Views:2370【SML】
Correct
choice of MOS tube is an important part of the MOS tube poor choice may
affect the efficiency and cost of the entire circuit to understand the
different MOS tube nuances of components and d...
label:
Correct
choice of MOS tube is an important part of the MOS tube poor choice may
affect the efficiency and cost of the entire circuit to understand the
different MOS tube nuances of components and different circuit switching
stress can help engineers to avoid many problems, The following and Polygalaceae together to learn the next MOS tube the right choice.
The first step: choose N-channel or P-channel
The first step in choosing the right device for a design is to decide whether to use N-channel or P-channel MOS transistors. In
a typical power application, when a MOS transistor is grounded and the
load is connected to mains voltage, the MOS transistor forms the low
side switch. In
low-side switches, N-channel MOS transistors should be used because of
the voltage required to turn off or turn on the device. When the MOS tube is connected to the bus and the load is grounded, it is necessary to use the high side switch. P-channel MOS transistors are often used in this topology for the sake of voltage-driven considerations.
To
choose the right device for your application, you must determine the
voltage required to drive the device and how to easily implement it in
your design. The next step is to determine the desired voltage rating or the larger voltage the device can withstand. The higher the rated voltage, the higher the cost of the device. According to practical experience, the rated voltage should be greater than the main line voltage or bus voltage. In order to provide adequate protection, MOS tube will not fail. In
the case of a MOS transistor of choice, it is necessary to determine
the larger voltage that the drain-to-source can withstand, ie a larger
VDS. It is important to know that the larger voltage a MOSFET can withstand varies with temperature. Designers must test the voltage range over the entire operating temperature range. The rated voltage must have sufficient margin to cover this range, to ensure that the circuit will not fail. Other
safety factors designers need to consider include voltage transients
induced by switching electronics such as motors or transformers. The voltage ratings vary for different applications; typically 20 V
for portable devices, 20-30 V for FPGA power, and 450-600 V for 85-220
VAC applications.
Step two: determine the rated current
The second step is to select the rated current MOS tube. Depending on the circuit structure, the rated current should be a large current that the load can withstand in all cases. Similar
to the case of voltage, the designer must ensure that the selected MOS
tube can withstand the rated current, even when the system generates a
spike current. The two considered current cases are continuous mode and pulse spikes. In
continuous conduction mode, the MOS transistor is in steady state, at
which point current continues to pass through the device. Pulse spikes refer to a large number of surges (or spikes) flowing through the device. Once a larger current is determined for these conditions, simply select the device that will withstand this larger current.
After selecting the rated current, you must also calculate the conduction loss. In
the actual situation, MOS tube is not the ideal device, because there
is electric energy loss in the course of the electric conduction, this
is called the conduction loss. The
MOSFET turns "on" as a variable resistor, as determined by the device's
RDS (ON), and varies significantly with temperature. The
power dissipation of the device can be calculated by Iload2 × RDS (ON).
As the on-resistance changes with temperature, the power dissipation
changes proportionally. The
higher the voltage VGS applied to the MOS transistor is, the smaller
the RDS (ON) will be, and the higher the RDS (ON) will be. For system designers, this is where trade-offs are needed depending on the system voltage. For
portable designs, it is easier (more common) to use lower voltages,
while for industrial designs, higher voltages can be used. Note that the RDS (ON) resistance increases slightly with current. A variety of electrical parameters on the RDS (ON) resistance can be found in the manufacturer's supplied technical data sheets.
Need
to remind designers, in general, MOS tube specification Id current is
the larger the normal current of the MOS chip, the actual use of the
larger normal current but also by the larger package current limit. Therefore, when designing a product, the larger current setting needs to consider the larger current limit of the package. It is more important to consider the MOS internal resistance
parameters when advising customers to design their products for greater
use.
Technology
has a significant impact on the features of the device, as some
techniques tend to increase RDS (ON) when raising larger VDSs. For
such a technology, if you plan to reduce VDS and RDS (ON), then you
have to increase the chip size, thereby increasing the package size and
associated development costs associated with it. There are several technologies available in the industry that
attempt to control the increase in the size of the wafers. The main ones
are trench and charge balancing techniques.
In
trench technology, a deep trench is embedded in the die, usually
reserved for low voltage, to reduce the on-resistance, RDS (ON). To reduce the impact of larger VDSs on RDS (ON), an epitaxial growth / etch column process was used during development. For
example, Fairchild Semiconductor has developed a technology called
SupeRFET that adds additional manufacturing steps to reduce RDS (ON). This
concern with RDS (ON) is important because RDS (ON) increases
exponentially as the breakdown voltage of a standard MOSFET increases,
resulting in an increase in the size of the wafer. The SuperFET process linearizes the exponential relationship between RDS (ON) and wafer size. This allows SuperFET devices to achieve the ideal low RDS (ON) at small die sizes, even at breakdown voltages up to 600V. The result is a 35% reduction in wafer size. For end users, this means a dramatic reduction in package size.
The third step: to determine the heat requirements
The next step in choosing a MOS transistor is to calculate the system's thermal requirements. Designers must consider two different situations, namely bad situations and real situations. It
is recommended that calculations be made for bad situations because
this result provides greater safety margin to ensure that the system
will not fail. MOS tube in the data sheet there are some need to pay attention
to the measurement data; such as the package of semiconductor junction
and the thermal resistance between the environment, and the larger
junction temperature.
The
junction temperature of the device equals the large ambient temperature
plus the product of thermal resistance and power dissipation (junction
temperature = ambient temperature + [thermal resistance × power
dissipation]). According
to this equation, the high power dissipation of the system can be
solved, which is equivalent to I2 × RDS (ON) by definition. RDS
(ON) at different temperatures can be calculated as the designer has
determined that a large current will be passed through the device. It is worth noting that designers must also consider the thermal
capacity of the semiconductor junction / device case and enclosure /
environment when dealing with simple thermal models; that is, require
the printed circuit board and package not to heat up immediately.
Avalanche
breakdown refers to the reverse voltage on the semiconductor device
exceeds a large value, and the formation of strong electric field so
that the device current increases. This current dissipates power, raises the temperature of the device, and may damage the device. Semiconductor
companies will avalanche test the device, calculate the avalanche
voltage, or to test the robustness of the device. There are two ways to calculate the rated avalanche voltage: one is statistical method and the other is thermal calculation. Thermal calculation is widely used because it is more practical. In addition to the calculation, the technique has a great influence on the avalanche effect. For example, an increase in wafer size increases resistance to avalanches and increases the robustness of the device. For the end user, this means using larger packages in the system.
Step four: determine the switch performance
The next step in choosing a MOS transistor is to determine the switching performance of the MOS transistor. There
are many parameters that affect the switching performance, but what is
important is the gate / drain, gate / source, and drain / source
capacitance. These capacitors create switching losses in the device because they are charged each time the switch is turned on. MOS tube switching speed is therefore reduced, the device efficiency also declined. To
calculate the total loss of the device during switching, the designer
must calculate the loss (Eon) during turn-on and the turn-off (Eoff)
during turn-on. The total power MOSFET switch can be expressed by the following equation: Psw = (Eon + Eoff) × switching frequency. The gate charge (Qgd) on the switching performance of a great influence.
2018-03-01
2370People browsing
Mobile website
